VHDL

-- VHDL example programme: hello.vhd
 
use std.textio.all;
 
entity hello is
end entity hello;
 
architecture Wiki of hello is
 
    constant message : string := "hello world";
 
begin
 
    process is
        variable L: line;
    begin
        write(L, message);
        writeline(output, L);
        wait;
    end process;
 
end architecture Wiki;

-- Fib.vhd
--
-- Fibonacci number sequence generator
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
 
entity Fibonacci is
port
(
    Reset       : in    std_logic;
    Clock       : in    std_logic;
    Number      : out   unsigned(31 downto 0)
);
end entity Fibonacci;
 
architecture Rcingham of Fibonacci is
 
    signal  Previous    : natural;
    signal  Current     : natural;
    signal  Next_Fib    : natural;
 
begin
 
    Adder:
    Next_Fib <= Current + Previous;
 
    Registers:
    process (Clock, Reset) is
    begin
        if Reset = '1' then
            Previous <= 1;
            Current  <= 1;
        elsif Clock'event and Clock = '1' then
            Previous <= Current;
            Current  <= Next_Fib;
        end if;
    end process Registers;
 
    Number <= to_unsigned(Previous, 32);
 
end architecture Rcingham;